Programmable integrated circuit devices such as field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and the like, may be used to implement a variety of functions. As an example, an FPGA device may be configured to perform various user functions based on different user designs.
Generally, an integrated circuit device includes a core region and a periphery region. A user design configuration may therefore be divided into two images: a core configuration image and a periphery configuration image. The core configuration image is used to configure logic elements or logic blocks in the core region while the periphery configuration image is used to configure peripheral elements such as input-output registers, transceiver blocks, etc.
To configure a device, a circuit designer may load the periphery image and the core image onto the device through a variety of available input-output protocols (e.g., the peripheral component interconnect express (PCIe) protocol). Typically, the circuit designer may modify and update the design at a later stage (e.g., in order to meet future application requirements), and may therefore load the updated core configuration image onto the device.
When the updated core configuration image is loaded onto the device, the device is reset. When the device is reset, application data or state information may be lost. Accordingly, once the device is reset, periphery settings that may be specific to the application (e.g., transceiver calibration information) are reset or overwritten with default settings even though the periphery configuration image has not been updated.
It is within this context that the embodiments described herein arise.